330 } else {
331 if (UseCRC32CIntrinsics) {
332 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
333 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
334 }
335 }
336 } else if (UseCRC32CIntrinsics) {
337 warning("CRC32C instruction is not available on this CPU");
338 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
339 }
340
341 if (UseVIS > 2) {
342 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
343 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
344 }
345 } else if (UseAdler32Intrinsics) {
346 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
347 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
348 }
349
350 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
351 (cache_line_size > ContendedPaddingWidth))
352 ContendedPaddingWidth = cache_line_size;
353
354 // This machine does not allow unaligned memory accesses
355 if (UseUnalignedAccesses) {
356 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
357 warning("Unaligned memory access is not available on this CPU");
358 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
359 }
360
361 #ifndef PRODUCT
362 if (PrintMiscellaneous && Verbose) {
363 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
364 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
365 tty->print("Allocation");
366 if (AllocatePrefetchStyle <= 0) {
367 tty->print_cr(": no prefetching");
368 } else {
369 tty->print(" prefetching: ");
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330 } else {
331 if (UseCRC32CIntrinsics) {
332 warning("SPARC CRC32C intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
333 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
334 }
335 }
336 } else if (UseCRC32CIntrinsics) {
337 warning("CRC32C instruction is not available on this CPU");
338 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
339 }
340
341 if (UseVIS > 2) {
342 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
343 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
344 }
345 } else if (UseAdler32Intrinsics) {
346 warning("SPARC Adler32 intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
347 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
348 }
349
350 if (UseOnSpinWaitIntrinsic) {
351 if (!FLAG_IS_DEFAULT(UseOnSpinWaitIntrinsic))
352 warning("onSpinWait intrinsic is not available on this CPU");
353 FLAG_SET_DEFAULT(UseOnSpinWaitIntrinsic, false);
354 }
355
356 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
357 (cache_line_size > ContendedPaddingWidth))
358 ContendedPaddingWidth = cache_line_size;
359
360 // This machine does not allow unaligned memory accesses
361 if (UseUnalignedAccesses) {
362 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
363 warning("Unaligned memory access is not available on this CPU");
364 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
365 }
366
367 #ifndef PRODUCT
368 if (PrintMiscellaneous && Verbose) {
369 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
370 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
371 tty->print("Allocation");
372 if (AllocatePrefetchStyle <= 0) {
373 tty->print_cr(": no prefetching");
374 } else {
375 tty->print(" prefetching: ");
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