1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2015 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "utilities/defaultStream.hpp"
35 #include "utilities/globalDefinitions.hpp"
36 #include "vm_version_ppc.hpp"
37
38 # include <sys/sysinfo.h>
39
40 int VM_Version::_features = VM_Version::unknown_m;
41 int VM_Version::_measured_cache_line_size = 32; // pessimistic init value
42 const char* VM_Version::_features_str = "";
43 bool VM_Version::_is_determine_features_test_running = false;
44
45
46 #define MSG(flag) \
47 if (flag && !FLAG_IS_DEFAULT(flag)) \
48 jio_fprintf(defaultStream::error_stream(), \
49 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
50 " -XX:+" #flag " will be disabled!\n");
51
52 void VM_Version::initialize() {
53
54 // Test which instructions are supported and measure cache line size.
55 determine_features();
56
57 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
58 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
59 if (VM_Version::has_lqarx()) {
60 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
61 } else if (VM_Version::has_popcntw()) {
62 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
63 } else if (VM_Version::has_cmpb()) {
64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
65 } else if (VM_Version::has_popcntb()) {
66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
67 } else {
68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
69 }
70 }
71 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 ||
72 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7 ||
73 PowerArchitecturePPC64 == 8,
74 "PowerArchitecturePPC64 should be 0, 5, 6, 7, or 8");
75
76 // Power 8: Configure Data Stream Control Register.
77 if (PowerArchitecturePPC64 >= 8) {
78 config_dscr();
79 }
80
81 if (!UseSIGTRAP) {
82 MSG(TrapBasedICMissChecks);
83 MSG(TrapBasedNotEntrantChecks);
84 MSG(TrapBasedNullChecks);
85 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
86 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
87 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
88 }
89
90 #ifdef COMPILER2
91 if (!UseSIGTRAP) {
92 MSG(TrapBasedRangeChecks);
93 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
94 }
95
96 // On Power6 test for section size.
97 if (PowerArchitecturePPC64 == 6) {
98 determine_section_size();
99 // TODO: PPC port } else {
100 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
101 }
102
103 MaxVectorSize = 8;
104 #endif
105
106 // Create and print feature-string.
107 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
108 jio_snprintf(buf, sizeof(buf),
109 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s",
110 (has_fsqrt() ? " fsqrt" : ""),
111 (has_isel() ? " isel" : ""),
112 (has_lxarxeh() ? " lxarxeh" : ""),
113 (has_cmpb() ? " cmpb" : ""),
114 //(has_mftgpr()? " mftgpr" : ""),
115 (has_popcntb() ? " popcntb" : ""),
116 (has_popcntw() ? " popcntw" : ""),
117 (has_fcfids() ? " fcfids" : ""),
118 (has_vand() ? " vand" : ""),
119 (has_lqarx() ? " lqarx" : ""),
120 (has_vcipher() ? " vcipher" : ""),
121 (has_vpmsumb() ? " vpmsumb" : ""),
122 (has_tcheck() ? " tcheck" : "")
123 // Make sure number of %s matches num_features!
124 );
125 _features_str = os::strdup(buf);
126 if (Verbose) {
127 print_features();
128 }
129
130 // PPC64 supports 8-byte compare-exchange operations (see
131 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
132 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
133 _supports_cx8 = true;
134
135 UseSSE = 0; // Only on x86 and x64
136
137 intx cache_line_size = _measured_cache_line_size;
138
139 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
140
141 if (AllocatePrefetchStyle == 4) {
142 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
143 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
144 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
145 } else {
146 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
147 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
148 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
149 }
150
151 assert(AllocatePrefetchLines > 0, "invalid value");
152 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
153 AllocatePrefetchLines = 1; // Conservative value.
154 }
155
156 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
157 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
158 }
159
160 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
161
162 // Implementation does not use any of the vector instructions
163 // available with Power8. Their exploitation is still pending.
164 if (!UseCRC32Intrinsics) {
165 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
166 FLAG_SET_DEFAULT(UseCRC32Intrinsics, true);
167 }
168 }
169
170 if (UseCRC32CIntrinsics) {
171 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics))
172 warning("CRC32C intrinsics are not available on this CPU");
173 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
174 }
175
176 // The AES intrinsic stubs require AES instruction support.
177 if (UseAES) {
178 warning("AES instructions are not available on this CPU");
179 FLAG_SET_DEFAULT(UseAES, false);
180 }
181 if (UseAESIntrinsics) {
182 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
183 warning("AES intrinsics are not available on this CPU");
184 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
185 }
186
187 if (UseGHASHIntrinsics) {
188 warning("GHASH intrinsics are not available on this CPU");
189 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
190 }
191
192 if (UseSHA) {
193 warning("SHA instructions are not available on this CPU");
194 FLAG_SET_DEFAULT(UseSHA, false);
195 }
196 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
197 warning("SHA intrinsics are not available on this CPU");
198 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
199 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
200 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
201 }
202
203 if (UseAdler32Intrinsics) {
204 warning("Adler32Intrinsics not available on this CPU.");
205 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
206 }
207
208 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
209 UseMultiplyToLenIntrinsic = true;
210 }
211
212 // Adjust RTM (Restricted Transactional Memory) flags.
213 if (!has_tcheck() && UseRTMLocking) {
214 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
215 // setting during arguments processing. See use_biased_locking().
216 // VM_Version_init() is executed after UseBiasedLocking is used
217 // in Thread::allocate().
218 vm_exit_during_initialization("RTM instructions are not available on this CPU");
219 }
220
221 if (UseRTMLocking) {
222 #if INCLUDE_RTM_OPT
223 if (!UnlockExperimentalVMOptions) {
224 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
225 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
226 } else {
227 warning("UseRTMLocking is only available as experimental option on this platform.");
228 }
229 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
230 // RTM locking should be used only for applications with
231 // high lock contention. For now we do not use it by default.
232 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
233 }
234 if (!is_power_of_2(RTMTotalCountIncrRate)) {
235 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
236 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
237 }
238 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
239 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
240 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
241 }
242 guarantee(RTMSpinLoopCount > 0, "unsupported");
243 #else
244 // Only C2 does RTM locking optimization.
245 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
246 // setting during arguments processing. See use_biased_locking().
247 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
248 #endif
249 } else { // !UseRTMLocking
250 if (UseRTMForStackLocks) {
251 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
252 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
253 }
254 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
255 }
256 if (UseRTMDeopt) {
257 FLAG_SET_DEFAULT(UseRTMDeopt, false);
258 }
259 if (PrintPreciseRTMLockingStatistics) {
260 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
261 }
262 }
263
264 // This machine does not allow unaligned memory accesses
265 if (UseUnalignedAccesses) {
266 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
267 warning("Unaligned memory access is not available on this CPU");
268 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
269 }
270 }
271
272 bool VM_Version::use_biased_locking() {
273 #if INCLUDE_RTM_OPT
274 // RTM locking is most useful when there is high lock contention and
275 // low data contention. With high lock contention the lock is usually
276 // inflated and biased locking is not suitable for that case.
277 // RTM locking code requires that biased locking is off.
278 // Note: we can't switch off UseBiasedLocking in get_processor_features()
279 // because it is used by Thread::allocate() which is called before
280 // VM_Version::initialize().
281 if (UseRTMLocking && UseBiasedLocking) {
282 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
283 FLAG_SET_DEFAULT(UseBiasedLocking, false);
284 } else {
285 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
286 UseBiasedLocking = false;
287 }
288 }
289 #endif
290 return UseBiasedLocking;
291 }
292
293 void VM_Version::print_features() {
294 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
295 }
296
297 #ifdef COMPILER2
298 // Determine section size on power6: If section size is 8 instructions,
299 // there should be a difference between the two testloops of ~15 %. If
300 // no difference is detected the section is assumed to be 32 instructions.
301 void VM_Version::determine_section_size() {
302
303 int unroll = 80;
304
305 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
306
307 // Allocate space for the code.
308 ResourceMark rm;
309 CodeBuffer cb("detect_section_size", code_size, 0);
310 MacroAssembler* a = new MacroAssembler(&cb);
311
312 uint32_t *code = (uint32_t *)a->pc();
313 // Emit code.
314 void (*test1)() = (void(*)())(void *)a->function_entry();
315
316 Label l1;
317
318 a->li(R4, 1);
319 a->sldi(R4, R4, 28);
320 a->b(l1);
321 a->align(CodeEntryAlignment);
322
323 a->bind(l1);
324
325 for (int i = 0; i < unroll; i++) {
326 // Schleife 1
327 // ------- sector 0 ------------
328 // ;; 0
329 a->nop(); // 1
330 a->fpnop0(); // 2
331 a->fpnop1(); // 3
332 a->addi(R4,R4, -1); // 4
333
334 // ;; 1
335 a->nop(); // 5
336 a->fmr(F6, F6); // 6
337 a->fmr(F7, F7); // 7
338 a->endgroup(); // 8
339 // ------- sector 8 ------------
340
341 // ;; 2
342 a->nop(); // 9
343 a->nop(); // 10
344 a->fmr(F8, F8); // 11
345 a->fmr(F9, F9); // 12
346
347 // ;; 3
348 a->nop(); // 13
349 a->fmr(F10, F10); // 14
350 a->fmr(F11, F11); // 15
351 a->endgroup(); // 16
352 // -------- sector 16 -------------
353
354 // ;; 4
355 a->nop(); // 17
356 a->nop(); // 18
357 a->fmr(F15, F15); // 19
358 a->fmr(F16, F16); // 20
359
360 // ;; 5
361 a->nop(); // 21
362 a->fmr(F17, F17); // 22
363 a->fmr(F18, F18); // 23
364 a->endgroup(); // 24
365 // ------- sector 24 ------------
366
367 // ;; 6
368 a->nop(); // 25
369 a->nop(); // 26
370 a->fmr(F19, F19); // 27
371 a->fmr(F20, F20); // 28
372
373 // ;; 7
374 a->nop(); // 29
375 a->fmr(F21, F21); // 30
376 a->fmr(F22, F22); // 31
377 a->brnop0(); // 32
378
379 // ------- sector 32 ------------
380 }
381
382 // ;; 8
383 a->cmpdi(CCR0, R4, unroll); // 33
384 a->bge(CCR0, l1); // 34
385 a->blr();
386
387 // Emit code.
388 void (*test2)() = (void(*)())(void *)a->function_entry();
389 // uint32_t *code = (uint32_t *)a->pc();
390
391 Label l2;
392
393 a->li(R4, 1);
394 a->sldi(R4, R4, 28);
395 a->b(l2);
396 a->align(CodeEntryAlignment);
397
398 a->bind(l2);
399
400 for (int i = 0; i < unroll; i++) {
401 // Schleife 2
402 // ------- sector 0 ------------
403 // ;; 0
404 a->brnop0(); // 1
405 a->nop(); // 2
406 //a->cmpdi(CCR0, R4, unroll);
407 a->fpnop0(); // 3
408 a->fpnop1(); // 4
409 a->addi(R4,R4, -1); // 5
410
411 // ;; 1
412
413 a->nop(); // 6
414 a->fmr(F6, F6); // 7
415 a->fmr(F7, F7); // 8
416 // ------- sector 8 ---------------
417
418 // ;; 2
419 a->endgroup(); // 9
420
421 // ;; 3
422 a->nop(); // 10
423 a->nop(); // 11
424 a->fmr(F8, F8); // 12
425
426 // ;; 4
427 a->fmr(F9, F9); // 13
428 a->nop(); // 14
429 a->fmr(F10, F10); // 15
430
431 // ;; 5
432 a->fmr(F11, F11); // 16
433 // -------- sector 16 -------------
434
435 // ;; 6
436 a->endgroup(); // 17
437
438 // ;; 7
439 a->nop(); // 18
440 a->nop(); // 19
441 a->fmr(F15, F15); // 20
442
443 // ;; 8
444 a->fmr(F16, F16); // 21
445 a->nop(); // 22
446 a->fmr(F17, F17); // 23
447
448 // ;; 9
449 a->fmr(F18, F18); // 24
450 // -------- sector 24 -------------
451
452 // ;; 10
453 a->endgroup(); // 25
454
455 // ;; 11
456 a->nop(); // 26
457 a->nop(); // 27
458 a->fmr(F19, F19); // 28
459
460 // ;; 12
461 a->fmr(F20, F20); // 29
462 a->nop(); // 30
463 a->fmr(F21, F21); // 31
464
465 // ;; 13
466 a->fmr(F22, F22); // 32
467 }
468
469 // -------- sector 32 -------------
470 // ;; 14
471 a->cmpdi(CCR0, R4, unroll); // 33
472 a->bge(CCR0, l2); // 34
473
474 a->blr();
475 uint32_t *code_end = (uint32_t *)a->pc();
476 a->flush();
477
478 double loop1_seconds,loop2_seconds, rel_diff;
479 uint64_t start1, stop1;
480
481 start1 = os::current_thread_cpu_time(false);
482 (*test1)();
483 stop1 = os::current_thread_cpu_time(false);
484 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
485
486
487 start1 = os::current_thread_cpu_time(false);
488 (*test2)();
489 stop1 = os::current_thread_cpu_time(false);
490
491 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
492
493 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
494
495 if (PrintAssembly) {
496 ttyLocker ttyl;
497 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
498 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
499 tty->print_cr("Time loop1 :%f", loop1_seconds);
500 tty->print_cr("Time loop2 :%f", loop2_seconds);
501 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
502
503 if (rel_diff > 12.0) {
504 tty->print_cr("Section Size 8 Instructions");
505 } else{
506 tty->print_cr("Section Size 32 Instructions or Power5");
507 }
508 }
509
510 #if 0 // TODO: PPC port
511 // Set sector size (if not set explicitly).
512 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
513 if (rel_diff > 12.0) {
514 PdScheduling::power6SectorSize = 0x20;
515 } else {
516 PdScheduling::power6SectorSize = 0x80;
517 }
518 } else if (Power6SectorSize128PPC64) {
519 PdScheduling::power6SectorSize = 0x80;
520 } else {
521 PdScheduling::power6SectorSize = 0x20;
522 }
523 #endif
524 if (UsePower6SchedulerPPC64) Unimplemented();
525 }
526 #endif // COMPILER2
527
528 void VM_Version::determine_features() {
529 #if defined(ABI_ELFv2)
530 // 1 InstWord per call for the blr instruction.
531 const int code_size = (num_features+1+2*1)*BytesPerInstWord;
532 #else
533 // 7 InstWords for each call (function descriptor + blr instruction).
534 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
535 #endif
536 int features = 0;
537
538 // create test area
539 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
540 char test_area[BUFFER_SIZE];
541 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
542
543 // Allocate space for the code.
544 ResourceMark rm;
545 CodeBuffer cb("detect_cpu_features", code_size, 0);
546 MacroAssembler* a = new MacroAssembler(&cb);
547
548 // Must be set to true so we can generate the test code.
549 _features = VM_Version::all_features_m;
550
551 // Emit code.
552 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
553 uint32_t *code = (uint32_t *)a->pc();
554 // Don't use R0 in ldarx.
555 // Keep R3_ARG1 unmodified, it contains &field (see below).
556 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
557 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
558 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
559 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
560 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
561 a->cmpb(R7, R5, R6); // code[4] -> cmpb
562 a->popcntb(R7, R5); // code[5] -> popcntb
563 a->popcntw(R7, R5); // code[6] -> popcntw
564 a->fcfids(F3, F4); // code[7] -> fcfids
565 a->vand(VR0, VR0, VR0); // code[8] -> vand
566 // arg0 of lqarx must be an even register, (arg1 + arg2) must be a multiple of 16
567 a->lqarx_unchecked(R6, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
568 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
569 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
570 a->tcheck(0); // code[12] -> tcheck
571 a->blr();
572
573 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
574 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
575 a->dcbz(R3_ARG1); // R3_ARG1 = addr
576 a->blr();
577
578 uint32_t *code_end = (uint32_t *)a->pc();
579 a->flush();
580 _features = VM_Version::unknown_m;
581
582 // Print the detection code.
583 if (PrintAssembly) {
584 ttyLocker ttyl;
585 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
586 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
587 }
588
589 // Measure cache line size.
590 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
591 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
592 int count = 0; // count zeroed bytes
593 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
594 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
595 _measured_cache_line_size = count;
596
597 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
598 VM_Version::_is_determine_features_test_running = true;
599 // We must align the first argument to 16 bytes because of the lqarx check.
600 (*test)((address)align_size_up((intptr_t)mid_of_test_area, 16), (uint64_t)0);
601 VM_Version::_is_determine_features_test_running = false;
602
603 // determine which instructions are legal.
604 int feature_cntr = 0;
605 if (code[feature_cntr++]) features |= fsqrt_m;
606 if (code[feature_cntr++]) features |= fsqrts_m;
607 if (code[feature_cntr++]) features |= isel_m;
608 if (code[feature_cntr++]) features |= lxarxeh_m;
609 if (code[feature_cntr++]) features |= cmpb_m;
610 if (code[feature_cntr++]) features |= popcntb_m;
611 if (code[feature_cntr++]) features |= popcntw_m;
612 if (code[feature_cntr++]) features |= fcfids_m;
613 if (code[feature_cntr++]) features |= vand_m;
614 if (code[feature_cntr++]) features |= lqarx_m;
615 if (code[feature_cntr++]) features |= vcipher_m;
616 if (code[feature_cntr++]) features |= vpmsumb_m;
617 if (code[feature_cntr++]) features |= tcheck_m;
618
619 // Print the detection code.
620 if (PrintAssembly) {
621 ttyLocker ttyl;
622 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
623 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
624 }
625
626 _features = features;
627 }
628
629 // Power 8: Configure Data Stream Control Register.
630 void VM_Version::config_dscr() {
631 assert(has_tcheck(), "Only execute on Power 8 or later!");
632
633 // 7 InstWords for each call (function descriptor + blr instruction).
634 const int code_size = (2+2*7)*BytesPerInstWord;
635
636 // Allocate space for the code.
637 ResourceMark rm;
638 CodeBuffer cb("config_dscr", code_size, 0);
639 MacroAssembler* a = new MacroAssembler(&cb);
640
641 // Emit code.
642 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->function_entry();
643 uint32_t *code = (uint32_t *)a->pc();
644 a->mfdscr(R3);
645 a->blr();
646
647 void (*set_dscr)(long) = (void(*)(long))(void *)a->function_entry();
648 a->mtdscr(R3);
649 a->blr();
650
651 uint32_t *code_end = (uint32_t *)a->pc();
652 a->flush();
653
654 // Print the detection code.
655 if (PrintAssembly) {
656 ttyLocker ttyl;
657 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
658 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
659 }
660
661 // Apply the configuration if needed.
662 uint64_t dscr_val = (*get_dscr)();
663 if (Verbose) {
664 tty->print_cr("dscr value was 0x%lx" , dscr_val);
665 }
666 bool change_requested = false;
667 if (DSCR_PPC64 != (uintx)-1) {
668 dscr_val = DSCR_PPC64;
669 change_requested = true;
670 }
671 if (DSCR_DPFD_PPC64 <= 7) {
672 uint64_t mask = 0x7;
673 if ((dscr_val & mask) != DSCR_DPFD_PPC64) {
674 dscr_val = (dscr_val & ~mask) | (DSCR_DPFD_PPC64);
675 change_requested = true;
676 }
677 }
678 if (DSCR_URG_PPC64 <= 7) {
679 uint64_t mask = 0x7 << 6;
680 if ((dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
681 dscr_val = (dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
682 change_requested = true;
683 }
684 }
685 if (change_requested) {
686 (*set_dscr)(dscr_val);
687 if (Verbose) {
688 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
689 }
690 }
691 }
692
693 static int saved_features = 0;
694
695 void VM_Version::allow_all() {
696 saved_features = _features;
697 _features = all_features_m;
698 }
699
700 void VM_Version::revert() {
701 _features = saved_features;
702 }